Joint Test Action Group (JTAG) refers to the IEEE 1149 standard for test access ports for testing printed circuit boards using boundary scan. JTAG is used by Automated Test Generation (ATG) tools to test printed circuit boards. Instrument JTAG (IJTAG) is now being standardized (referred to as the IEEE P1687 standard) to overcome existing JTAG limitations associated with the move from board-level JTAG to chip-level JTAG. IJTAG proposes inclusion of dynamic hierarchical paths inside data registers using dynamic hierarchical cells, such as the cell referred to as the Select Instrument Bit (SIB) cell. The use of dynamic hierarchical paths enables portions of the scan path to be turned on and off as needed. Thus, dynamic hierarchical paths that are enabled by use of cells like the SIB are a valuable testing resource because, as the number of elements in the scan path is important in determining testing time, careful use of hierarchy may be used to reduce testing time.
As described in the proposed IEEE P1687 standard, the scan chain is a linear scan chain and each SIB cell that is inserted into the scan chain is inserted in order to introduce hierarchy into the scan chain. Thus, since the scan chain is linear, and each SIB cell included in the linear scan chain must be accessed linearly via the scan chain in order to activate hierarchy in the scan chain, the length of the scan chain directly determines the amount of access time needed to modify and exercise the active hierarchy. While this limitation may seem insignificant in examples in which the scan chain only includes a few cells, this may be a significant limitation in real-life systems where the scan chain may include hundreds or even thousands of cells. While the impact of this problem may be reduced by use of accurate scheduling of testing procedures, this problem simply cannot be completely avoided by use of scheduling of testing procedures.